1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more specifically, to a circuit arrangement for facilitating a test of an integrated circuit device.
2. Description of Prior Art
The integration degree of semiconductor integrated circuit devices is every increasing as represented by VLSI's and ULSI's, so that the operational test such as D.C. characteristics test and A.C. characteristics test become more complex. At present, therefore, a serious problem is how to carry out the testings easily. As one of circuit design techniques circuits for facilitating the test of IC's, a scan-pass type test circuit has been proposed and put into practical use.
FIG. 1 shows a semiconductor integrated circuit device (IC), 100 equipped with a conventional the scan-path type test circuit. Symbols I.sub.1, I.sub.2, I.sub.K-1 to I.sub.K+1, and I.sub.m denote input terminals, reference numerals 31 to 33 denote logic gate combination circuits or data processing circuits, 34 and 35 denote registers. A scan-path may be formed by circuitting the combination circuits I.sub.1 to I.sub.k+1 and the registers 35 and 35. Symbols F.sub.11 to F.sub.1l and F.sub.21 to F.sub.2r denote flip-flops composing the registers 34 and 35. Symbols S.sub.11 to S.sub.1P, S.sub.21 to S.sub.2l, S.sub.31 ro S.sub.3Q and S.sub.42 to S.sub.4r denote signal lines, O.sub.1 to O.sub.n denote output terminals, S.sub.IN denotes a shift-in (scan-in) terminal, S.sub.IN1 denotes a shift-in signal line, S.sub.OUT denotes a shift-out (scan-out) terminal, S.sub.OUT1 denotes a shift-out signal line of the register 34 and a shift-in signal line for the register 35, S.sub.OUT2 denotes a shift-out signal line, and SMD is a designation signal for designating either one of a normal operating mode and a test mode, CLOCK denotes a clock terminal, C.sub.LK1 denotes a clock signal line, and FB1 and FB2 denote feedback data lines.
When the signal SMD designates the normal operating mode, each of the registers 34 and 35 operates as a parallel register: or a temperary register. Under this mode, the first logic circuit 31 receives input data from the terminals I.sub.1 to I.sub.m and feedback data from the lines FB1 and FB2 to perform predetermined operations on these data. Some of output data from the circuit 31 are temporarily stored in the register 34 in synchronism with the clock CLOCK and then supplied to the second logic circuit 32. The remaining output data are directly supplied to the second logic circuit 32. If desired, the register 34 can temporarily store the remaining output data. The second logic circuit 32 performs predetermined operations on the supplied data. Similarly, some of the output data from the circuit 32 are temporarily stored in the other register 35 in synchronism with the clock and supplied to the third logic circuit 33. The remaining output data are directly supplied to the third logic circuit 3. Selected data stored in the register 35 is further fed back to the first circuit 1. While the circuit 33 performs predetermined operations on the data supplied thereto, the output data therefrom are supplied to the output terminals Q.sub.1 to Q.sub.n.
On the other hand, the signal SMD designates the test mode, each of the registers 34 and 35 operates as a shift register. Under this mode, the test data is supplied to the registers 34 and 35 from the shift-in terminal SIN in synchronism with the clock signal supplied to the terminal CLOCK. After the desired test data are set into the registers 34 and 35, the IC 100 is brought into the normal operating mode with the input test data being supplied to the terminals I.sub.1 to I.sub.m. While the logic circuit 31, performs operations on the input test data, the other logic circuits 32 and 33 perform operations the test data supplied from the registers 34 and 35, respectively. the result data derived from the circuits 31 and 32 are stored again in the registers 34 and 35, respectively, to be read out from the terminals O.sub.1 to O.sub.n through the shift register constructed by the registers 34 and 35. The operations of IC 100 is checked by the result data derived from the registers 34 and 35 through the shift-out terminal S.sub.OUT in synchronism with the clock signal. Thus, the operational tests of the logic circuits 31 to 33 can be carried out independently of each other, so that the operational test of the IC 100 is facilitated.
However, this IC 100 requires a very long test time for carrying out A.C. characteristic test. More specifically, the IC 100 includes a critical data propagation path requiring very long time for propagating data therethrough. In the A.C. characteristic test, the data propagation delay time on this critical path should be measured. The data propagates through the critical path only when the circuits 31, 32 and 33 satisfy particular conditions. To this end, complicated test data are required to be set in the IC 100 a plurality times. For this reason, a long A.C. test time is required.